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Combinational Logic

Boolean Properties

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Identity & Null $A$ AND with itself or its inverse.

$A \cdot A = A$ $A \cdot \overline{A} = 0$

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OR Properties $A$ OR with itself or its inverse.

$A + A = A$ $A + \overline{A} = 1$

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Absorption Classic simplification.

$A \cdot (A + B) = A$ $A + (A \cdot B) = A$

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De Morgan Inverting complex expressions.

$\overline{A \cdot B} = \overline{A} + \overline{B}$ $\overline{A + B} = \overline{A} \cdot \overline{B}$ $\overline{A \oplus B} = \overline{A} \oplus B = A \oplus \overline{B}$

CMOS Technology

Gate Structure:

Each input is connected to 1 NMOS and 1 PMOS.

PMOS (top, with bubble): Conducts if $G a t e = 0$ .

NMOS (bottom): Conducts if $G a t e = 1$ .

Operation:

If PMOS conducts $\to$ Output = 1 (VDD).

If NMOS conducts $\to$ Output = 0 (GND).

Dual Topology:

If 2 PMOS in series $\to$ 2 NMOS in parallel.

If 2 PMOS in parallel $\to$ 2 NMOS in series.

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Specific Logic Gates

XOR (Exclusive OR)

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Definition and identities of XOR.

$A \oplus B = (A \cdot \overline{B}) + (\overline{A} \cdot B)$ $A \oplus A = 0$ $A \oplus \overline{A} = 1$ $A \oplus 0 = A$ $A \oplus 1 = \overline{A}$

XNOR (Equivalence)

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Inverse of XOR.

$\overline{A \oplus B} = A \cdot B + \overline{A} \cdot \overline{B}$ $\overline{A \oplus B} = \overline{A} \oplus B = A \oplus \overline{B}$

Multiplexer (MUX 2:1)

Selects $A$ or $C$ based on $B$ .
$Y = (A \cdot \overline{B}) + (C \cdot B)$

Minterms vs Maxterms

Minterms and Maxterms are used to express the Boolean functions in its canonical forms.

Minterms ( $y = 1$ ): Sum of Products (SOP), the output is equal to 1

Maxterms ( $y = 0$ ): Product of Sums (POS), the output is equal to 0

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Sequential Logic

Latches

SR Latch (Set-Reset)

Asynchronous Latch.

Set Priority: $Q = S + \overline{R} \cdot Q$ (if $S = 1, R = 1 \to Q = 1$ ).

Reset Priority: $Q = \overline{R} \cdot (S + Q)$ (if $S = 1, R = 1 \to Q = 0$ ).

D-Latch

Level sensitive.

Transparent when $E = 1$ (or Clock high).

$Q = \overline{E} \cdot Q_{p re v} + E \cdot D$

Flip-Flops

D-FlipFlop

Edge sensitive (Rising or falling edge).

Built with two D-Latches in series (Master-Slave).

No “Gated Clock” allowed.

Timing Constraints

Temporal Definitions:

$T_{c l k}$ : Clock period.

$t_{p}$ : Propagation delay ( $t_{l o g i c} + t_{w i re}$ ).

Duty Cycle: $\frac{T _{hi g h}}{T _{p er i o d}}$ .

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Timing Analysis

Setup Time ( $t_{se t u p}$ ) Time before the clock edge where data $D$ must be stable.

Hold Time ( $t_{h o l d}$ ) Time after the clock edge where data $D$ must remain stable.

Stability Conditions:
If $D$ changes within the window $(t_{c l oc k} - t_{se t u p}, t_{c l oc k} + t_{h o l d})$ , the flip-flop enters Metastability (indeterminate state 0 or 1).

Critical Path

The critical path determines the maximum frequency.

$T_{min} \geq t_{se t u p} + t_{p ro p_d e l a y} + t_{l o g i c_ma x}$

Number Systems

Signed Representations

Sign-Magnitude:

MSB = Sign ( $0 = +, 1 = -$ ).

Rest = Magnitude.

Issue: Two zeros ( $+ 0, - 0$ ).

1’s Complement:

Positive: Same as Sign-Mag.

Negative: Total bit inversion (NOT).

Issue: Two zeros.

2’s Complement:

Negative: Total inversion + 1.

Only one zero. Standard.

Excess-N (Biased):

$X_{s t ore d} = X_{re a l} + N$ .

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Karnaugh & FSM

Karnaugh Map Method

Used to simplify combinational logic.

Draw the grid: $2^{N}$ cells (Gray Code: 00, 01, 11, 10).

Fill: Place 1s from the truth table.

Group: Powers of 2 ( $1, 2, 4, 8...$ ). Largest groups possible.

Sum: $Y = \sum (terms of groups)$ .

Example 3 vars: $Y = \overline{A} \cdot B + \overline{B} \cdot \overline{D}$

Finite State Machine (FSM)

Design Steps

State Diagram: Define states (circles) and transitions (arrows).

Completeness & Consistency:

Completeness: At least one active transition possible.

Consistency: At most one active transition at a time.

State Encoding:

Number of bits $N \geq ⌈ lo g_{2} (Number of states)⌉$ .

Transition table (Current State $\to$ Next State).

Logic:

Transition Logic (Next State Logic).

Output Logic.
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Moore vs Mealy

Moore FSM

Outputs depend only on the current state.
flowchart LR
    I[Inputs] --> L1[Transition Logic]
    L1 --> R[State Reg]
    R -->|Current State| L1
    R --> L2[Output Logic]
    L2 --> O[Outputs]
Output synchronous with state.

Mealy FSM

Outputs depend on current state AND inputs.
flowchart LR
    I[Inputs] --> L1[Transition Logic]
    I ----> L2
    L1 --> R[State Reg]
    R -->|Current State| L1
    R --> L2[Output Logic]
    L2 --> O[Outputs]
Output asynchronous (reacts immediately to inputs).

Generic Circuit

Transition Logic: Pure combinational. Determines $D_{0}, D_{1} ...$

State Memory: Flip-Flops ( $Q_{0}, Q_{1} ...$ ).

Output Logic: Determines final output.

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