Bus systems

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Purpose and Fundamental concepts

HW interfacing to a peripheral costs time, goal is to reduce latency
➡️ We do this by I/O abstraction and thoughtful topologies
A bus can be serial or parallel
A parallel bus is the fastest way to transfer data. It features three categories of signals: address; data; control. the data
must be addressed before being transferred (what data is required). Memory generally must know whether
data is being read from the device or being written to, therefore control systems are required.

Bottleneck in computing are external peripherals

Memory, Graphics, I/O devices, slow memory

Topologies and history

Stage	Name	Key Idea	Example Bus
1	ISA-Driven (Separate I/O & Memory space)	CPU has special I/O instructions & separate I/O bus	Old x86 ISA bus (IN/OUT instructions)
2	Memory-Mapped (Single unified address space)	I/O devices mapped into memory address space	ARM, RISC-V SoCs, STM32 registers
3	Processor-Driven (CPU controls bus timing)	Timing of external bus tied directly to CPU clock	Early microcontrollers, 8086 external bus
4	Processor-Independent Bus	A bridge separates CPU bus from external I/O bus	PCI / PCIe systems, Northbridge/Southbridge
5	Multi-Level (Hierarchical)	Fast internal bus + slower peripheral bus levels	AMBA (AHB, APB), Wishbone, Tilelink

AMBA - Advanced Microprocessor Bus Architecture

Series of specifications of bus systems for SoC architecture. Originally two parts: a system level bus and a peripheral level bus. Slow peripherals feature a cheaper bus.
Three relevant version :

• AMBA-2: AHB, APB
• AMBA-3: AXI, ATB
• AMBA-4 AXI4, AXU-Lite, AXI-Stream

flowchart TB
  subgraph AHB_MASTERS
    CPU[CPU Core]
    DMA[DMA Controller]
  end

  subgraph AHB_BUS[AHB Bus / Interconnect]
    ARB[Arbiter]
    DEC[Address Decoder]
  end

  subgraph AHB_SLAVES
    SRAM[SRAM]
    FLASH[Flash]
    BRIDGE[AHB to APB Bridge]
  end

  subgraph APB_BUS[APB Bus]
    GPIO[GPIO]
    UART[UART]
    TIMER[Timers]
  end

  %% Connections
  CPU --> ARB
  DMA --> ARB
  ARB --> DEC
  DEC --> SRAM
  DEC --> FLASH
  DEC --> BRIDGE

  BRIDGE --> GPIO
  BRIDGE --> UART
  BRIDGE --> TIMER

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AHB
High performance
Pipelined operation
Burst transfer
Multiple bus masters
Split transactions

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APB
Low power and easy to access
Not pipelined (one transfer at a time)
Suitable for many peripherals

Architectures

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Harvard Architecture

Separate busses for code and data
✅ Avoids mutual exclusion
❌ Higher chip costs

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Modified Harvard

Separate data and code paths internally (different cache), Joined code and data paths externally (RAM, ROM)
✅Best of both world
❌More complex

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von Neumann Architecture

Combines data and code on one bus
✅Cheaper processors
❌Increase risk of mutual exclusion, von Neumann bottleneck (can’t fetch instruction and read/write at same time)

AHB and bus operations

Note

Beat (in bus transfers)

• One unit of data transferred per clock cycle on the bus.
• If the bus is 32 bits wide → one beat = 32 bits per cycle.

A bus transaction is simply:

1. Master puts an address on the address lines.

2. Master sets read/write control.

3. Bus decoder selects the target slave.

4. Slave responds with either:

   • Data (for read), or
   • Acceptance (for write).

5. Handshake signals confirm completion.
   Short version:
   Master requests → Address decoded → Slave responds → Transfer completes.
   Arbitration → Addressing → Data → Confirmation.

Summary

Bus has its own clock
Bus indicates type of cycle
Bus indicate the size of the transfer
Bus can keep a peripheral active for sequential addressing
Bus can insert wait-cycles
Device can request wait-cycles (to facilitate when busy)
Device can indicate whether the transfer was successful
Devices comply to bus
Bus is a master-slave operation
Bus requires a default-slave when idle

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AHB bus instructions

Operation / Mode	Bus Type	Who Initiates	Behavior	When Used	Notes
Read	AHB / APB	Master	Reads data from selected slave	Fetching data / status	Standard single read
Write	AHB / APB	Master	Writes data to selected slave	Config registers / memory	Standard single write
Burst Read	AHB	Master	Multiple sequential reads in one transfer	DMA memory loading	High throughput
Burst Write	AHB	Master	Multiple sequential writes	DMA memory storing	Reduces bus overhead
Idle Cycle	AHB	Master	No data transfer	Pause / no operation	Uses HTRANS=IDLE
Busy Cycle	AHB	Master	Master keeps bus but does not progress	Temporary delay	Maintains ownership
Peripheral Register Access	APB	Master	Single non-pipelined read/write	GPIO, UART, Timers, I2C	Low power/low complexity
Wait / Stall	AHB / APB	Slave	Slave delays completion	Flash or slow peripheral	Uses HREADY/PREADY
Cycle-Stealing DMA	AHB	DMA	DMA takes one bus cycle at a time between CPU cycles	Audio, UART streams	CPU still runs, slight slowdown
Transparent DMA	AHB	DMA	DMA transfers only when bus is idle	Low-priority data movement	CPU sees zero performance hit
Fly-By Transfer	AHB / AXI	Master→Slave bypass	Data goes from source to destination without buffering in DMA	High-speed peripherals (SDIO/ETH)	Reduces latency + buffer requirements

Signal	Direction (Master/Slave)	Type / Purpose	Width	Description
HCLK	Global	Clock	1	Main bus clock for all transfers
HRESETn	Global	Reset (active low)	1	Resets bus logic and interfaces
HADDR	Master → Slave	Address lines	32	Address for read/write transaction
HWDATA	Master → Slave	Write data	32/64	Data being written to slave
HWRITE	Master → Slave	Control	1	1 = Write, 0 = Read
HSIZE	Master → Slave	Control	3	Transfer size (byte/half/word/etc.)
HBURST	Master → Slave	Control	3	Burst type (single, incrementing, wrap)
HPROT	Master → Slave	Control	4	Privilege/cache/security attributes
HTRANS	Master → Slave	Control	2	Transaction type (IDLE, BUSY, NONSEQ (start of burst), SEQ)
HMASTLOCK	Master → Slave	Control	1	Locks bus during atomic sequences
HRDATA	Slave → Master	Read data	32/64	Data returned by the selected slave
HREADY	Slave → Master	Handshake	1	Indicates slave is ready (0 = wait)
HRESP	Slave → Master	Response	1–2	Transfer OK/ERROR indication